It is known for packets containing control information and video information, to be provided to a video decoder that is being able to process real time moving video images and that includes,
decoding means deriving from at least said video information new units of decoded video information relating to a current video frame; PA1 a memory module in which said new units are stored; PA1 display means displaying said stored new units on a video screen.
Such a video decoder is well known in the art, e.g. from the article "Variable Bit Rate Video Codec for asynchronous transfer mode networks", by W. Verbiest and L. Pinnoo, IEEE Journal on selected areas in communications, Vol. 7, No 5, June 1989, pp, 761-770 and more particularly point II.E "VBR Decoder" and FIG. 8 thereof, the latter figure-showing a block schematic of such a video decoder.
As all known video decoders of the above type, the referenced decoder works synchronously with its corresponding encoder, i.e. the clock signal controlling the latter encoder is reproduced by the decoder and used to control the decoder. This synchronous operation is up to now assumed to be mandatory for real time video processing of moving video images sent over packet switching networks. The reason therefore is given in the article "Packet Video integration into network architecture" by Karlsson and Vitterbi, which appeared in the same issue of the above Journal, and more particularly in point V on pp 745-746 "Resynchronization of video" thereof. Without this synchronous operation the decoder could indeed process the packets too fast or too slow with respect to the generation of packets by the encoder. When working too fast, as depicted in FIG. 8b of the last referenced article, the decoder would have to discard packets arriving too late to be taken into account for the reconstruction of an image, When working too slow, as depicted in FIG. 8c, an ever increasing number of packets would have to be buffered by the decoder, inevitably leading to buffer overflow and hence again to packet loss.
Apart from the above mentioned need for synchronous working of the encoder and the decoder, the latter decoder has also to take into account possible jitter inherent to asynchronous transfer mode networks and caused by a variable transmission delay of the packets over the network, which additionally complicates the structure and design of the decoder. Indeed, in order to operate synchronously with its corresponding encoder, the decoder has to perform its decoding actions at well-defined instants in time determined by the system clock of the encoder. Due to the above jitter it could however occur that a packet arrives too late to be processed at the above instant. To avoid this, the packets arriving at the decoder are stored in an input buffer, where they are delayed to achieve for every packet a fixed predetermined delay, as depicted in FIG. 7 of the last referenced article. In this way the input buffer acts as a dejittering unit which is read under control of the decoder clock, the latter clock being reconstructed by means of for instance a phase locked loop to match the encoder clock. Due to the statistical nature of the delay jitter packet loss cannot be avoided with finite input buffers and finite fixed delays as evidenced by FIG. 8a of the last referenced article; minimizing this packet loss requires relatively large input buffers.
Referring again to the first referenced article by W. Verbiest and L. Pinnoo the consequence of the above mentioned need for synchronization and dejittering is made clear.
The decoding means described in the article includes a Variable Length Code decoder (VLC Decoder) and a Differential Pulse Code Modulation Decoder (DPCH Decoder). The latter decoder is controlled by a RAM module using the control information extracted from the packet by a depacketizer and uses a memory module, called a frame store memory, to decode predictively coded video information, i.e. video informtion relating to a previous frame is stored in the memory module and used to predict corresponding video information of a new frame. The display means is schematically represented as a Digital to Analog Converter (DAC) and a monitor or video screen. The above mentioned need for synchronization results in the use of a Digital Phase Locked Loop (DPLL), whilst the need for dejittering results in the use of a dejittering unit or input buffer. The latter input buffer has to be dimensioned in order to reduce packet loss caused by the delay jitter and will typically have to be large enough to store video packets corresponding to one half of a video frame.
Summarizing, a drawback of video decoders of the type disclosed in the latter article is that the structure thereof is rather complex due to the circuitry needed for synchronization of the decoder clock with the encoder clock, e.g. by using a phase locked loop, and for elimination of the delay jitter for which a relatively large input buffer is needed. Moreover such decoders are rather inflexible due to the timing constraints resulting from the synchronous operation of the decoding means and the display means with respect to each other, as is clear from the mentioned articles.